Electronic packages are interconnectable housings for integrated circuit (IC) devices. Packaging is performed after a semiconductor wafer has been fabricated according to known semiconductor processing techniques, and then “diced” (i.e., cut) into individual IC “chips”. Typically, packaging involves placing one or more IC chips into a package housing, electrically connecting the IC chip to contact pads formed on the housing, e.g., by wire bonding these contact pads to corresponding input/output (I/O) die bonding pads formed on the IC chip(s), and then covering the IC chip and wire bonds for protection. The housings typically include multiple leads, pins, or bumps that are connected by conductive traces to the contact pads, and are arranged in a predetermined pattern such that the packaged IC chip can be tested by applying test signals to the leads/pins/bumps using a test fixture. Faulty IC chips are thus identified and discarded, while IC chips that pass this testing process are subsequently mounted (e.g., soldered) onto a corresponding contact site of another host system printed circuit board (PCB). If a packaged IC subsequently fails, the faulty IC can be removed from the host system by heating the solder to remove the faulty IC, cleaning the PCB contact site, and then resoldering a new packaged IC onto the contact site.
A problem associated with the conventional practice of packaging IC chips prior to testing is that the process of packaging damaged or otherwise non-functional IC chips significantly increases overall production costs. Currently, there are few chip-scale socket solutions capable of testing IC chips prior to packaging. Instead, most IC test socket technology consists of zero insertion force (ZIF) sockets, which are designed to facilitate the insertion and removal of a dual in-line package or pin grid array package without special tools. As such, these conventional ZIF socket solutions require packaging of each IC chip before they can be used, which increases overall manufacturing costs and thus reduces profitability.
Therefore, compliant, reworkable IC chip connections are a highly desired technology for testing and burning in the IC chips prior to packaging. In addition to making assembly and rework simpler and faster, such connections could facilitate the circumvention of tariffs on imported computer parts (e.g., lap top computers can be shipped separately from their processors, and hence get taxed as parts rather than as completed computer systems).
Flip-chip technology is growing in popularity because of its high input/output density capability, increased chip-packaging density, and excellent electrical performance. Solder-bumped, flip-chip technology has been well established since IBM developed the C4 process. In this process, solder bumps were formed on under-bump metallurgy (UBM) pads on the chip and joined to matching metal pads on the substrate by a reflow process. Because the established technique involves difficult and expensive processes to implement, new low-cost techniques for flip chip connections were sought.
Recently, the stud-bump bonding (SBB) technology, which is based on the wire-bonding technology, has been developed as a very attractive solution for a low-cost flip-chip technology. With SBB technology, gold stud bumps are placed on the die bond pads of IC chips through a modification of the “ball bonding” process used in conventional wire bonding. In ball bonding, the tip of the gold bond wire is melted to form a sphere. The wire-bonding tool presses this sphere against the aluminum bond pad, applying mechanical force, heat, and ultrasonic energy to create a metallic connection. The wire-bonding tool next extends the gold wire to the connection pad on the board, substrate, or lead frame, and makes a “stitch” bond to that pad, finishing by breaking off the bond wire to begin another cycle. For gold stud bumping, the first ball bond is made as described, but the wire is then broken close above the ball. The resulting gold ball with truncated wire, or “stud bump”, remains on the bond pad to provide a permanent, reliable connection through the aluminum oxide to the underlying metal. This technology has several advantages: UBM process is not necessary, bumping cost is low, and fine-pitch and chip-level bumping is possible.
Gold stud bump flip chip technology offers several advantages over conventional IC packaging. The bumping equipment, a wire bonder or dedicated stud bumper, is widely available and well characterized. Since stud bumps are formed by wire bonders, they can be placed anywhere a wire bond might be placed. They can easily achieve pitches of less than 100 microns and be placed on pads of less than 75 microns. Since stud bumping can be done on a wire bonder, it does not require wafers or under-bump metallization (UBM). Single, off-the-shelf die can be bumped and flipped without pre-processing. This makes the stud bump flip chip model fast, efficient, and flexible for product development, prototyping and low to medium volume production, while easy to scale up to high volume wafer-based production with automated equipment.
Although stud bumping is fairly well developed, what is not yet established is a connection socket that can receive stud bumps in a reliable and reworkable manner.
Therefore, what is needed is a compliant and reworkable connection socket for electrically connecting stud bumped IC devices to a host system (e.g., a testing system, or a PCB of an electronic device).